Architecture of Microprocessor,General architecture,Harvard architecture.

General Architecture of microprocessor

Microprocessor architecture defines suitable placement of its various functional blocks in the form of required circuitry for efficient flow of data and result from one block to another.

the general purpose architecture of microprocessor is shown in figure:

Architecture of microprocessor contains:

ALU(Arithmetic Logical Unit):It contains of an adder,an accumulator,a temporary register,and a shift register and a status register.

This ALU unit performs various arithmetic and logic operation.

General purpose register:

In the microprocessor,there are 8-bit general purpose register or as a 16-bit register pairs,when used in register pair mode .

These are used for both storing data as well as the aaddress.

Special purpose register : This consists of accumulator,Program counter (PC),Stack pointer(SP) and status flag register.

These register are used for some specific applications designated by the manufacturers.

Instruction decoder : This receives the contents of instruction registers and develops control signals that enable data paths necessary to execute the instruction.

Timing and control unit: This unit controls and synchronizes all the operations inside and outside the microprocessor.

The timing and control signals are derived from the master clock.

The control unit also accepts the control signals generated by the other devices associated with microprocessor system.

Address bus: This is used for transmitting address information.

The address bus will normally contain 16-bits to provide for addessing and addressing capability of up to 64kB of memory.

Control bus: This comprises of various signal lines used for carrying synchronization signals.The microprocessor uses such lines for providing timing signals.

HARVARD ARCHITECTURE OF MICROPROCESSOR

Harward architecture uses separate memories for program and data with their independent address and data buses.

Because of two different streams of data and address,there is no need to have any time division multiplexing of address and data buses.

Not only the architeture supports parallel buses for address and data,but also it allows a different internal organization such that instruction can be prefetched and decoded while multiple data are being fetched and operated on.

Further,the data bus may have different size than the address bus.This allows the optimal  bus widhts of the data and address buses for fast execution of the intruction.

EXAMPLE

MCS-51 family of microcontrollers by Intel has Harward architecture because there are different memory spaces for program and data and separate (internal) buses for address and data.

PIC microcontrollers by microchip use Harvard architecture.